Process design kits (PDKs)
A PDK is the bridge between a design and a foundry. It is the foundry-validated library of components, models, and rules that ties your layout to a specific fabrication process — so what you draw is something that can actually be made.
Photonic chips are manufactured on a particular process at a particular foundry: a fixed material platform, layer stack, and set of lithographic capabilities. A process design kit (PDK) packages everything you need to design for that process. It is the contract between you and the fab — a curated set of building blocks that the foundry has characterized and committed to producing within known tolerances.
Designing against a PDK is what keeps a layout grounded in physical reality. Instead of drawing arbitrary geometry and hoping it is manufacturable, you assemble devices the process is known to support, connect them with waveguides the process can pattern, and stay inside rules the foundry guarantees. In Qfactr the PDK is always present: it sits in the left panel alongside the searchable component library, and every part you place carries the physical information that makes it behave like a real device.
What a PDK is
A PDK is a foundry-validated library of components plus the design rules and process information needed to use them correctly. It is tied to one specific fabrication process — change the foundry or the platform (silicon photonics on SOI, silicon nitride, indium phosphide, thin-film lithium niobate) and you change the PDK. The kit encodes both what you can build and the constraints under which you can build it.
The point of a PDK is manufacturability. Each component has been measured or rigorously modeled on real silicon, so its optical behavior and physical footprint are trustworthy rather than idealized. Designing to a PDK means designing to what a foundry can actually make, which is the difference between a layout that taped out and one that only worked in theory.
What's inside
Different foundries package PDKs differently, but the same categories of content recur across photonic processes:
| Element | What it is | Why it matters |
|---|---|---|
| Parameterized cells (PCells) | Component layouts driven by parameters — for example a ring resonator whose radius, gap, and waveguide width are inputs rather than fixed geometry. | One validated cell covers a family of devices; changing a parameter regenerates correct, rule-clean geometry. |
| Compact / S-parameter models | The optical behavior of each component, captured as a compact model or an S-matrix (S-parameter) description across wavelength. | Lets you predict transmission, loss, and coupling without re-running full electromagnetic simulation for every part. |
| Design rules (DRC) | Constraints the process imposes: minimum widths and spacings, minimum bend radius, enclosure and density requirements. | Violating them risks a part the foundry cannot reliably pattern or that behaves outside its spec. |
| Layer map / layer stack | The mapping from drawn shapes to physical fabrication layers, plus the vertical stack the process defines. | Ensures geometry lands on the right masks so the chip is built as intended. |
PCells and S-parameter models are what let a layout double as a circuit description. Because a component knows both its footprint and its frequency-domain response, the same design can drive layout export and circuit simulation — see Components & building blocks for the device catalog and Simulation-aware design for how that response feeds back into the canvas.
Design rules and DRC
Design rule checking (DRC) verifies that a layout obeys the geometric constraints of its process before it goes to the mask shop. In photonics those rules are not only about lithographic resolution; they are also about optics. A bend tighter than the process minimum radius radiates power; a waveguide narrower than the rule width may not guide a single mode; insufficient spacing between waveguides creates unintended coupling. Many photonic design rules are simultaneously manufacturability rules and performance rules.
PDKs in Qfactr
Qfactr is PDK-aware: the parts you place are not abstract symbols. Each component from the library carries its physical pin positions and S-matrix (S-parameter) data, so it occupies a true footprint in micrometers and responds to light the way the real device does. Pins are physical ports with real coordinates, which is why routes are drawn as real waveguide geometry between them and why transmission and loss can be derived directly from the path you build. This is the foundation of the representation layer: layout, connectivity, and physics live in one editable model.
Every new workspace starts with a Demo-PDK so you can begin designing immediately — search the library, place parts at real micron coordinates, and route between their pins without first wiring up an external process kit. The Demo-PDK is meant for learning the workflow and exploring the tool, not for committing a specific tape-out.
When a design is ready to leave the workspace, the PDK-backed geometry and models are what make a clean handoff possible. You export the layout to Nazca and GDS for fabrication and the circuit description to S-parameter simulators, so the design moves into the fab flow your team already runs without losing its physical grounding.